The following abbreviations are hereinafter employed in the specification, as are other standard industry terms:
3GPP3rd Generation Partnership ProjectAWGNAdditive White Gaussian NoiseBSBase StationCPICHCommon Pilot ChannelDLDownlinkFDDFrequency Division DuplexFIRFinite Impulse ResponseH/WHardwareIIn-phasePARPeak-to-Average RatioPSCPrimary Synchronisation CodePLPPhysical Layer ProcessorQQuadrature-phaseSSCSecondary Synchronisation CodeSCHSynchronisation ChannelSRShift RegisterUEUser EquipmentW-CDMAWideband Code-Division Multiple Access
When UE is powered on, the UE has no knowledge of the system timing of a transmitting cell. The 3GPP W-CDMA FDD standard specifies an initial cell search procedure to synchronise the UE reception timing to that of the serving cell.
The initial cell search procedure includes three steps, namely: slot synchronisation; frame synchronisation and codegroup identification; and scrambling-code identification.
Generally, the goal of slot synchronisation is to obtain the slot timing reference by analysis of synchronisation sequences transmitted in each cell by the system. Frame synchronisation and codegroup identification is used to determine the transmitting frame boundary as well as the codegroup to which the primary scrambling code belongs. Scrambling-code identification is used to identify the primary scrambling code used by the base station (BS) to transmit a common pilot channel (CPICH).
The Synchronisation Channel (SCH), being the synchronisation sequence, is a downlink signal that consists of two sub-channels, the Primary and Secondary SCH. The 10 ms radio frames of the Primary and Secondary SCH are divided into 15 slots, each having a length of 2560 chips. FIG. 1 illustrates the general structure of the SCH radio frame. The primary synchronisation code (PSC) is the same for each cell, and the secondary synchronisation code (SSC) is different for each cell. PSC is intended to achieve slot synchronisation whilst SSC is adopted to achieve frame synchronisation.
The first step in the baseband for the UE to synchronise to the serving cell is to perform an initial cell search. There are altogether three steps in a cell search procedure. This invention is directed towards the first step of the cell search, namely slot synchronisation.
The principle used in slot synchronisation is to perform correlation over the received PSC. This correlation is repeated for as long as the length of a slot, i.e., 2560 chip duration. A profile of 2560 locations in a slot is then constructed. By determining the peak of the profile, the slot boundary can be determined.
Examination on the PSC sequence suggests that a FIR of length 256 is necessary to perform the correlation. However, such an FIR requires a large piece of hardware for realisation. In order to reduce the cost of implementation, it is necessary to look for other possibilities of reducing hardware requirements while maintaining acceptable performance.
This identifies a need for a new method of slot synchronisation which overcomes the problems inherent in the prior art.